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rk3399 jtag 2020-08-17

in uboot reconfigure the IOs to JTAG - mw.l 0xff77e024 0xffff05a5

Error: 435 49 aarch64.c:2324 aarch64_examine_first(): rk3399.t0: examination failed

???

Info : SWD DPIDR 0x5ba02477
Info : rk3399.a53.0: hardware has 6 breakpoints, 4 watchpoints
Info : rk3399.a53.1: hardware has 1 breakpoints, 1 watchpoints
Error: rk3399.a53.2: examination failed

openocd script below mostly pasted together from https://metebalci.com/blog/bare-metal-raspberry-pi-3b-jtag/

adapter speed 1000
transport select swd

set _CHIPNAME rk3399
set _TARGETNAME $_CHIPNAME.t

set _ENDIAN little

swd newdap rk3399 cpu -enable
dap create $_CHIPNAME.dap -chain-position $_CHIPNAME.cpu

set DBGBASE {0x80030000 0x80031000 0x80032000 0x80034000 0x80210000 0x80310000}
set CTIBASE {0x80038000 0x80039000 0x8003a000 0x8003b000 0x80220000 0x80320000}

set _TARGETNAME $_CHIPNAME.a53
set _CTINAME $_CHIPNAME.cti

set _cores 4

for { set _core 0 } { $_core < $_cores } { incr _core } {

    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
        -ctibase [lindex $CTIBASE $_core]

    target create $_TARGETNAME.$_core aarch64 \
        -dap $_CHIPNAME.dap -coreid $_core \
        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core

    $_TARGETNAME.$_core configure -event reset-assert-post "aarch64 dbginit"
}

set _TARGETNAME $_CHIPNAME.a72
set _cores 6
for { set _core 4 } { $_core < $_cores } { incr _core } {
    cti create $_CTINAME.$_core -dap $_CHIPNAME.dap -ap-num 1 \
        -ctibase [lindex $CTIBASE $_core]

    target create $_TARGETNAME.$_core aarch64 \
        -dap $_CHIPNAME.dap -coreid $_core \
        -dbgbase [lindex $DBGBASE $_core] -cti $_CTINAME.$_core

    $_TARGETNAME.$_core configure -event reset-assert-post "aarch64 dbginit"
}

Here's the ROM table for the APB MEM-AP that all the debug stuff is supposed to hang off of:

> rk3399.dap info 1
AP ID register 0x44770002
	Type is MEM-AP APB
MEM-AP BASE 0x80000003
	Valid ROM table present
		Component base address 0x80000000
		Peripheral ID 0x0000080000
		Designer is 0x080, <invalid>
		Part is 0x0, Unrecognized 
		Component class is 0x1, ROM table
		MEMTYPE system memory not present: dedicated debug bus
	ROMTABLE[0x0] = 0x1003
		Component base address 0x80001000
		Peripheral ID 0x04002bb908
		Designer is 0x4bb, ARM Ltd.
		Part is 0x908, CoreSight CSTF (Trace Funnel)
		Component class is 0x9, CoreSight component
		Type is 0x12, Trace Link, Funnel, router
	ROMTABLE[0x4] = 0x3003
		Component base address 0x80003000
		Peripheral ID 0x04004bb906
		Designer is 0x4bb, ARM Ltd.
		Part is 0x906, CoreSight CTI (Cross Trigger)
		Component class is 0x9, CoreSight component
		Type is 0x14, Debug Control, Trigger Matrix
	ROMTABLE[0x8] = 0x4003
		Component base address 0x80004000
		Peripheral ID 0x04001bb101
		Designer is 0x4bb, ARM Ltd.
		Part is 0x101, Unrecognized 
		Component class is 0xf, PrimeCell or System component
	ROMTABLE[0xc] = 0x5003
		Component base address 0x80005000
		Peripheral ID 0x04004bb912
		Designer is 0x4bb, ARM Ltd.
		Part is 0x912, CoreSight TPIU (Trace Port Interface Unit)
		Component class is 0x9, CoreSight component
		Type is 0x11, Trace Sink, Port
	ROMTABLE[0x10] = 0x20003
		Component base address 0x80020000
		Peripheral ID 0x04004bb4a3
		Designer is 0x4bb, ARM Ltd.
		Part is 0x4a3, Cortex-A53 ROM (v7 Memory Map ROM Table)
		Component class is 0x1, ROM table
		MEMTYPE system memory not present: dedicated debug bus
	[L01] ROMTABLE[0x0] = 0x10003
		Component base address 0x80030000
		Peripheral ID 0x04004bbd03
		Designer is 0x4bb, ARM Ltd.
		Part is 0xd03, Cortex-A53 Debug (Debug Unit)
		Component class is 0x9, CoreSight component
		Type is 0x15, Debug Logic, Processor
	[L01] ROMTABLE[0x4] = 0x11003
		Component base address 0x80031000
		Peripheral ID 0x04004bb9d3
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
		Component class is 0x9, CoreSight component
		Type is 0x16, Performance Monitor, Processor
	[L01] ROMTABLE[0x8] = 0x12003
		Component base address 0x80032000
		Peripheral ID 0x04004bbd03
		Designer is 0x4bb, ARM Ltd.
		Part is 0xd03, Cortex-A53 Debug (Debug Unit)
		Component class is 0x9, CoreSight component
		Type is 0x15, Debug Logic, Processor
	[L01] ROMTABLE[0xc] = 0x13003
		Component base address 0x80033000
		Peripheral ID 0x04004bb9d3
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
		Component class is 0x9, CoreSight component
		Type is 0x16, Performance Monitor, Processor
	[L01] ROMTABLE[0x10] = 0x14003
		Component base address 0x80034000
		Peripheral ID 0x04004bbd03
		Designer is 0x4bb, ARM Ltd.
		Part is 0xd03, Cortex-A53 Debug (Debug Unit)
		Component class is 0x9, CoreSight component
		Type is 0x15, Debug Logic, Processor
	[L01] ROMTABLE[0x14] = 0x15003
		Component base address 0x80035000
		Peripheral ID 0x04004bb9d3
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
		Component class is 0x9, CoreSight component
		Type is 0x16, Performance Monitor, Processor
	[L01] ROMTABLE[0x18] = 0x16003
		Component base address 0x80036000
		Peripheral ID 0x04004bbd03
		Designer is 0x4bb, ARM Ltd.
		Part is 0xd03, Cortex-A53 Debug (Debug Unit)
		Component class is 0x9, CoreSight component
		Type is 0x15, Debug Logic, Processor
	[L01] ROMTABLE[0x1c] = 0x17003
		Component base address 0x80037000
		Peripheral ID 0x04004bb9d3
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9d3, Cortex-A53 PMU (Performance Monitor Unit)
		Component class is 0x9, CoreSight component
		Type is 0x16, Performance Monitor, Processor
	[L01] ROMTABLE[0x20] = 0x18003
		Component base address 0x80038000
		Peripheral ID 0x04004bb9a8
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
		Component class is 0x9, CoreSight component
		Type is 0x14, Debug Control, Trigger Matrix
	[L01] ROMTABLE[0x24] = 0x19003
		Component base address 0x80039000
		Peripheral ID 0x04004bb9a8
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
		Component class is 0x9, CoreSight component
		Type is 0x14, Debug Control, Trigger Matrix
	[L01] ROMTABLE[0x28] = 0x1a003
		Component base address 0x8003a000
		Peripheral ID 0x04004bb9a8
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
		Component class is 0x9, CoreSight component
		Type is 0x14, Debug Control, Trigger Matrix
	[L01] ROMTABLE[0x2c] = 0x1b003
		Component base address 0x8003b000
		Peripheral ID 0x04004bb9a8
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9a8, Cortex-A53 CTI (Cross Trigger)
		Component class is 0x9, CoreSight component
		Type is 0x14, Debug Control, Trigger Matrix
	[L01] ROMTABLE[0x30] = 0x1c003
		Component base address 0x8003c000
		Peripheral ID 0x04004bb95d
		Designer is 0x4bb, ARM Ltd.
		Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
		Component class is 0x9, CoreSight component
		Type is 0x13, Trace Source, Processor
	[L01] ROMTABLE[0x34] = 0x1d003
		Component base address 0x8003d000
		Peripheral ID 0x04004bb95d
		Designer is 0x4bb, ARM Ltd.
		Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
		Component class is 0x9, CoreSight component
		Type is 0x13, Trace Source, Processor
	[L01] ROMTABLE[0x38] = 0x1e003
		Component base address 0x8003e000
		Peripheral ID 0x04004bb95d
		Designer is 0x4bb, ARM Ltd.
		Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
		Component class is 0x9, CoreSight component
		Type is 0x13, Trace Source, Processor
	[L01] ROMTABLE[0x3c] = 0x1f003
		Component base address 0x8003f000
		Peripheral ID 0x04004bb95d
		Designer is 0x4bb, ARM Ltd.
		Part is 0x95d, Cortex-A53 ETM (Embedded Trace)
		Component class is 0x9, CoreSight component
		Type is 0x13, Trace Source, Processor
	[L01] ROMTABLE[0x40] = 0x0
	[L01] 	End of ROM table
	ROMTABLE[0x14] = 0x200003
		Component base address 0x80200000
		Peripheral ID 0x04000bb4a4
		Designer is 0x4bb, ARM Ltd.
		Part is 0x4a4, Cortex-A72 ROM (ROM Table)
		Component class is 0x1, ROM table
		MEMTYPE system memory not present: dedicated debug bus
	[L01] ROMTABLE[0x0] = 0x10003
		Component base address 0x80210000
		Peripheral ID 0x04000bbd08
		Designer is 0x4bb, ARM Ltd.
		Part is 0xd08, Cortex-A72 Debug (Debug Unit)
		Component class is 0x9, CoreSight component
		Type is 0x15, Debug Logic, Processor
	[L01] ROMTABLE[0x4] = 0x20003
		Component base address 0x80220000
		Peripheral ID 0x04004bb906
		Designer is 0x4bb, ARM Ltd.
		Part is 0x906, CoreSight CTI (Cross Trigger)
		Component class is 0x9, CoreSight component
		Type is 0x14, Debug Control, Trigger Matrix
	[L01] ROMTABLE[0x8] = 0x30003
		Component base address 0x80230000
		Peripheral ID 0x04000bb9d8
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9d8, Cortex-A72 PMU (Performance Monitor Unit)
		Component class is 0x9, CoreSight component
		Type is 0x16, Performance Monitor, Processor
	[L01] ROMTABLE[0xc] = 0x40003
		Component base address 0x80240000
		Peripheral ID 0x04000bb95a
		Designer is 0x4bb, ARM Ltd.
		Part is 0x95a, Cortex-A72 ETM (Embedded Trace)
		Component class is 0x9, CoreSight component
		Type is 0x13, Trace Source, Processor
	[L01] ROMTABLE[0x10] = 0x110003
		Component base address 0x80310000
		Peripheral ID 0x04000bbd08
		Designer is 0x4bb, ARM Ltd.
		Part is 0xd08, Cortex-A72 Debug (Debug Unit)
		Component class is 0x9, CoreSight component
		Type is 0x15, Debug Logic, Processor
	[L01] ROMTABLE[0x14] = 0x120003
		Component base address 0x80320000
		Peripheral ID 0x04004bb906
		Designer is 0x4bb, ARM Ltd.
		Part is 0x906, CoreSight CTI (Cross Trigger)
		Component class is 0x9, CoreSight component
		Type is 0x14, Debug Control, Trigger Matrix
	[L01] ROMTABLE[0x18] = 0x130003
		Component base address 0x80330000
		Peripheral ID 0x04000bb9d8
		Designer is 0x4bb, ARM Ltd.
		Part is 0x9d8, Cortex-A72 PMU (Performance Monitor Unit)
		Component class is 0x9, CoreSight component
		Type is 0x16, Performance Monitor, Processor
	[L01] ROMTABLE[0x1c] = 0x140003
		Component base address 0x80340000
		Peripheral ID 0x04000bb95a
		Designer is 0x4bb, ARM Ltd.
		Part is 0x95a, Cortex-A72 ETM (Embedded Trace)
		Component class is 0x9, CoreSight component
		Type is 0x13, Trace Source, Processor
	[L01] ROMTABLE[0x20] = 0x0
	[L01] 	End of ROM table
	ROMTABLE[0x18] = 0x0
		End of ROM table

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